The present invention relates to data communication circuits having multiple interfaces which arbitrate for a single resource. More particularly, the present invention relates to a priority control circuit for controlling the arbitration.
Data communication circuits such as network devices and telecommunication circuits typically have several communication channels for connecting to multiple devices such as workstations, telephone and television systems, video teleconferencing systems and other facilities over common data links or carriers. In these applications, it is common for all communication channels to share a common resource, such as a system memory. Each channel includes a data interface controller, such as a serial wide area network (SWAN) controller or a local area network (LAN) controller. The data interface controller is coupled to the shared resource for controlling transmission of the data over the data link or carrier.
Data interface controllers are often configured to transmit packets of data having an arbitrary length at a fixed speed. For example, a WAN controller may transmit an Internet Protocol (IP) packet over an fixed speed ISDN Basic Rate Interface (BRI) using high level data length control (HDLC) framing. Alternatively, a LAN controller such as an Ethernet controller may transmit an IP packet a fixed speed 10 Mbps LAN. A direct memory access (DMA) controller is often used for arbitrating access to the shared resource among multiple data interface controllers.
A first-in-first-out (FIFO) buffer has been used for buffering transmit and receive data between the DMA controller and each data interface controller. During a transmit operation, the DMA controller feeds the data packets to one end of the FIFO at a DMA transmission rate, and the data interface controller reads the packets at the other end of the FIFO at the rate of the fixed speed data interface. The FIFO is needed because the DMA transmission rate is generally substantially higher on average than the rate of the fixed speed data interface. Also, the DMA controller is subject to "gaps" in its ability to feed the FIFO because of memory access latencies, contention with other master devices that are coupled to the memory bus and control logic overhead.
Each FIFO is accompanied by control logic that requests service from the DMA controller when the amount data in the FIFO drops below a certain point. This amount is chosen such that even with worst-case memory access latency, bus contention and control overhead, the data in the FIFO will not be completely drained by the fixed speed data interface. This results in a relatively large FIFO.
In silicon application specific integrated circuit (ASIC) implementations, the area on the integrated circuit die that is dedicated to FIFO memory is very expensive compared to the memory typically used for an off-chip memory such as a dynamic random access memory (DRAM). It is therefore advantageous to be able to implement the smallest FIFO possible while maintaining the ability to pass data without risking FIFO underruns. This task is made more complex when multiple data interfaces exist and each data interface requires access to the same DMA controller to pull data from an external, off-chip memory.
The traditional approach for keeping in the FIFO size small even with multiple data interfaces competing for the same DMA controller has been to create a multiple priority scheme. In such a scheme, the FIFO associated with each data interface provides a signal to an arbitration logic block that indicates its priority. In a two priority system, FIFOs that contain only a small amount of data are closer to experiencing an underrun condition and therefore signal a "high priority" arbitration request to the arbitration block. FIFOs that contain relatively more data are not as close to experiencing an underrun condition and therefore signal a "normal priority" arbitration request to the arbitration logic. Such a system ensures that FIFOs that need service urgently get serviced sooner than FIFOs that need service less urgently. In effect, FIFOs that contain more data are less likely to get even more data from the DMA controller because other FIFOs with less data are able to assert the high priority arbitration request. This serves to lower the peak FIFO size.
However, such systems require the fixed speed data interface to be configured to start extracting data from the FIFO only after a set amount of data is in the FIFO. This point is referred to as a "start threshold". If the fixed speed data interface is allowed to extract data from the FIFO as soon as the first bit of data is stored in the FIFO from the DMA controller, the FIFO will have very little tolerance for DMA controller delays that may be occasioned by memory access latencies, bus contention and control logic overhead. If the FIFO runs out of data before the entire data packet has been transmitted, a FIFO underrun occurs which corrupts the transmission. The amount of data that needs to be in the FIFO before the fixed speed data interface is allowed to begin extracting data from the FIFO is calculated to accommodate the worst-case DMA controller delays.
The traditional method of implementing the multiple priority scheme suffers from a key deficiency. In a situation where multiple fixed speed data interfaces exist, each with their own logical FIFO channel, it is fairly common to have all of the FIFO's arbitrating at high priority simultaneously. This situation occurs when all of the fixed speed data interfaces begin transmitting a data packet at one time. At the beginning of a transmission, all of the FIFOs will be nearly empty, and will therefore arbitrate at high priority. This means that, in the worst-case, one of the FIFOs will have to wait for the DMA controller to satisfy all of the other FIFOs' requests for data before its own request is satisfied, despite having its "high priority" flag asserted. Because this adds to the worst-case time before the FIFO gets serviced, it increases where the "start threshold" needs to be set. This adds to the FIFO size because the FIFO needs to be at least as the largest of the thresholds computed for the FIFO. A second deficiency of the higher "start threshold" is that system latency increases because the fixed speed data interface is not permitted to start its transmission until more data has accumulated in the FIFO.
The data communication and priority control circuit of the present invention addresses these and other problems and offers other advantages over the prior art.